FIG. 1 is a circuit diagram of a semiconductor device according to the background art, particularly of a data output circuit portion of a MOS memory on a semiconductor chip which has a set of power source terminals to supply a power source voltage and a ground voltage to the MOS memory. In FIG. 1, the circuit portion enclosed by a broken line indicates an internal circuit A implemented on semiconductor chip. The power source voltage is applied across the power source terminals T1 and T2. An address of a memory is supplied to an address input terminal T4. Data is outputted from a data output terminal T3. The level "1"(high) or "0" (low) of an output data at the data output terminal T3 is determined by the level "1" or "0" of an output data drive signal d or d supplied to the gates of output transistors (e.g., N-channel transistors) implemented on the semiconductor chip. Namely, when the output data drive signal d of "1" level is applied to the transistor 11, this transistor 11 becomes conductive and outputs a data of level "1". On the other hand, when the output data drive signal d of "1" level is applied to the transistor 12, this transistor 12 becomes conductive and outputs a data of level "0".
There are various parasitic elements outside of the semiconductor chip, such as those derived from the package, external wirings and the like. Specifically, on the side of the power source voltage terminal T1, there are an integrated circuit external parasitic resistor 13 and an integrated circuit external parasitic inductor. On the side of the ground voltage terminal T2, there are an integrated circuit external parasitic resistor 14 and an integrated circuit external parasitic inductor 17. In addition to such parasitic elements, on the side of the data output terminal T3, there are an integrated circuit external parasitic inductor 18, an integrated circuit parasitic resistor 15, and a load capacitor 110. Within the semiconductor chip, there is an integrated circuit internal inter-terminal capacitor 19 between the power source voltage terminal T1 and the ground voltage terminal T2. A d.c. power source 111 is connected across the power source voltage terminal T1 and ground voltage terminal T2 for supplying power therebetween.
With the circuit arrangement described above, there will be described the case where the output level at the data output terminal T3 changes from "1" to "0". In this case, the level of the output data drive signal d changes from "low" to "high" to make the output transistor 12 conductive. When this transistor 12 becomes conductive, electric charge in the load capacitor 110 is discharged through a path I routing from the data output terminal T3 to the output transistor 12. This discharge current Id flows through the parasitic resistors 14 and 15 and parasitic inductors 17 and 18 at the path I so that noise is generated on the ground voltage terminal T2. Current also flows through a path II via the capacitor 19 so that this current also generates noise on the power source voltage terminal T1.
The change of voltage waveforms, during such operation, at the power source voltage terminal T1, ground voltage terminal T2, and data output terminal T3 is shown in FIG. 2. As seen from FIG. 2, as the level at the data output terminal T3 changes from "1" to "0", noise is generated on the terminals T1 and T2.
Next, there will be described the case where the output level at the data output terminal T3 changes from "0" to "1". In this case, the level of the output data drive signal d changes from "low" to "high" to make the output transistor 11 conductive. When this transistor 11 becomes conductive, electric charge in the load capacitor 110 is charged through a path III routing via the output transistor 11 to the data output terminal T3, as shown in FIG. 3. This charge current Ic flows through the parasitic resistors 13 and 15 and parasitic inductors 16 and 18 at the path III so that noise is generated on the power source voltage terminal T1. Current also flows through a path VI via the capacitor 19 within the semiconductor chip so that this current also generates noise on the ground voltage terminal T2.
The change of voltage waveforms, during such operation, at the power source voltage terminal T1, ground voltage terminal T2, and data output terminal T3 is shown in FIG. 4. As seen from FIG. 4, as the level at the data output terminal T3 changes from "0" to "1", noise is generated on the terminals T1 and T2.
As described above, when the level at the data output terminal T3 changes from "0" to "1" or from "1" to "0", charge or discharge current flows to or from the load capacitor 110 so that noise is generated on the power source voltage terminal T1 and ground voltage terminal T3. These noises are particularly noticeable when the levels of all of a plurality of output data terminals of a semiconductor memory chip change from "0" to "1" or from "1" to "0" at the same time. Noise generated at the power source voltage terminal T1 and ground voltage terminal T3 results in noise at the address input terminal T4. Thus, an address is recognized erroneously, resulting in erroneous operation and data output delay.
As a method of solving the above problems, there is known a semiconductor device wherein power is supplied from different power source terminals to an output buffer unit and the other internal circuit of a semiconductor chip.
FIG. 5 is a block diagram of a circuit of such a semiconductor device. As shown in FIG. 5, there are provided, within the semiconductor chip 8 enclosed by a one-dot-chain line, a power source voltage terminal T1 and a ground voltage terminal T2 as well as an output buffer transistor V.sub.DD terminal T5 and V.sub.SS terminal T6. Output transistors 11 and 12 are independently powered from the V.sub.DD terminal T5 and V.sub.SS terminal T6. An internal circuit enclosed by a broken line is powered from the terminals T1 and T2.
In the internal circuit A, an inverter buffer IV1 outputs an output data drive signal d and an inverter buffer IV2 outputs an output data drive signal d, in response to an address data from an address terminal T4. An integrated circuit inner inter-terminal capacitor 54 is present as a parasitic capacitor between the V.sub.DD terminal T5 and V.sub.SS terminal T6. There are also present an integrated circuit external parasitic inductor 51 and parasitic resistor 46 between the V.sub.DD terminal T5 and a d.c. power source 111. There are also present an integrated circuit external parasitic resistor 47 and parasitic inductor 52 between the V.sub.SS terminal and the d.c. power source 111. In FIG. 5, like elements to those shown in FIGS. 1 and 3 are represented by using identical reference numerals.
With the semiconductor device constructed as above, a change of an output data level at the data output terminal T3 from "1" to "0" occurs when the output transistor 12 becomes conductive upon reception of the output data drive signal d. In this case, discharge current Id from the load capacitor 110 flows through a path Ia routing from the data output terminal T3 to the output transistor 12 and to the V.sub.SS terminal V.sub.SS T6. However, this current Id does not flow to the terminals T1 and T2. Therefore, noise will not be generated on the terminals T1 and T2.
On the other hand, a change of the output level at the data output terminal T3 from "0" to "1" occurs when the output transistor 11 turned on upon receipt of the output data drive signal d. In this case, charge current Ic to the load capacitor 110 flows through a path IIIa routing from the V.sub.DD terminal T5 to the output transistor 11 and to the data output terminal T3. However, this charge current does not flow to the terminals T1 and T2. Therefore, noise will not be generated on the terminals T1 and T2.
With the circuit arrangement shown in FIG. 5, it is therefore possible to prevent noise from appearing at the address input terminal T4 from which an address signal is supplied to the internal circuit A.
With the integrated circuit semiconductor device constructed as shown in FIG. 5, for example, if data of "1" level is being outputted from the data output terminal T3, the output transistor 11 is in a conductive state. As the output transistor 11 becomes conductive, current flows through the path IIIa so that noise appears at the V.sub.DD terminal T5. The potential at the V.sub.DD terminal T5 therefore lowers so that current flows through the capacitor 54 resulting in similar noise at the V.sub.SS terminal T6. The potential at the terminal T6 therefore lowers. In this case, there is the possibility that the actual low level of the output data drive signal d becomes high level as viewed from the V.sub.SS terminal, resulting in an erroneous conducting in the output transistor 12. Such erroneous operation may cause a delay of the output data at the data output terminal T3 or an erroneous output data.